A) Field of the Invention
The present invention relates to a display device substrate and its manufacture method, and more particularly to a display device active matrix substrate having thin film transistors and its manufacture method.
B) Description of the Related Art
Liquid crystal display devices and organic EL display devices have been used recently as flat panel display devices. The functions of a display device can be improved by using an active matrix having a switching element (active element) for each display pixel. Such an active matrix substrate is widely used with a personal computer (PC), a portable phone and the like.
When thin film transistors are formed on a glass substrate, an amorphous silicon film is used at the early stage because of a limit of a heat resistance temperature of the glass substrate. Recently, high performance polysilicon transistors having a mobility improved much more than that of an amorphous silicon transistor can be manufactured by polycrystallizing an amorphous silicon film or depositing a polysilicon film directly. If a polysilicon film is used, a peripheral circuit can be mounted on the same substrate. In association with this arrangement, developments aiming at a higher performance and lower consumption power are now in progress.
FIG. 22 shows an example of the structure of an active matrix substrate. A display area DA for display and a peripheral circuit area PH, adjacent to a display area, for peripheral circuits are defined on an insulating transparent substrate SUB such as a glass substrate. In the display area DA, a plurality of scanning gate wiring lines (bus lines) GL for scanning extend along a row (horizontal) direction and a plurality of image data wiring lines (bus lines) DL for image data supply extend along a column (vertical) direction.
At each cross point between the scanning gate wiring line GL and image data wiring line DL, a thin film transistor is connected whose output terminal is connected to a pixel electrode PX made of a transparent electrode such as ITO. One electrode of a supplemental capacitor SC is connected to each pixel element PX. The other electrode of the supplemental capacitor SC is connected to a supplemental capacitor wiring line (bus line) SCL maintained at a constant potential. In the structure shown in FIG. 22, although the supplemental capacitor wiring lines SCL extend along the row direction, they may extend along the column direction.
In the display area DA, pixels are disposed in a matrix shape as described above, and each pixel has the pixel electrode PX for controlling display. The scanning gate wiring line GL is disposed along the pixel row and the image data wiring line DL is disposed along the pixel column. The thin film transistor TFT controlled to be turned on and off by the scanning gate wiring line GL supplies the pixel electrode PX with image data from the image data wring line DL. As the thin film transistor TFT turns on, the pixel electrode PX retains the image data together with the supplemental capacitor SC.
Formed in the peripheral circuit area PH are: a gate driver GD for generating a scan signal group to be supplied to the scanning gate wiring lines; a data driver DD for supplying image data to the image data wiring lines; and a display controller DC for receiving a control signal CS from an external and controlling the gate driver GD and data driver DD. The gate driver GD includes a shift register SR1, a level shifter LS1, an output buffer OB and the like. The data driver DD includes a shift register SR2, a level shifter LS2, an analog switch AS and the like. Reference voltages VL and VH and an image signal ID are supplied from an external.
In an active matrix substrate integrated with peripheral circuits, the display controller DC and shift registers SR1 and SR2 are required to operate at relatively high speed. The level shifters LS1 and LS2, output buffer OB and analog switch AS are required to operate at relatively high voltage and have a high breakdown voltage.
The switching thin film transistors (TFT) used in the display area are required to have a relatively high breakdown voltage. Even if TFTs in the display area are made of only n-channel TFTs, the peripheral circuit PH is preferably made of CMOS circuits. Therefore, in addition to n-channel TFTs, p-channel TFTs are also formed. If all TFTs are formed by using the same gate insulating film, the thickness of the gate insulating film is set same as that of a high breakdown voltage TFT. A MOS capacitor is generally used as the supplemental capacitor in a display device circuit using polysilicon.
FIGS. 23A to 23G are cross sectional views of main processes illustrating one example of a conventional method of manufacturing CMOS thin film transistors and supplemental capacitors used in the circuit shown in FIG. 22.
As shown in FIG. 23A, on a transparent insulating substrate 100 such as a glass substrate, an SiN layer of 50 nm in thickness and an SiO layer of 200 nm in thickness are deposited by chemical vapor deposition (CVD) to form a buffer layer 101. On the buffer layer 101, an amorphous silicon film is deposited by CVD and polycrystallized into a polysilicon film by annealing with excimer laser. A polysilicon film may be deposited directly. After the polysilicon film is formed, it is patterned into an island silicon layer 102 by photolithography and etching. Three island silicon films shown in FIG. 23A are used for a p-channel TFT, an n-channel TFTs and a supplemental capacitor, starting from the left.
As shown in FIG. 23B, an SiO layer 103 of 120 nm in thickness covering the island silicon films 102 is deposited by CVD to form a gate insulating film. On the insulating gate film 103, an Mo layer 104 of 300 nm in thickness is deposited by physical vapor deposition (PVD) such as sputtering, and patterned by photolithography and etching to form electrodes 104. The two electrodes on the left side are gate electrodes and one electrode on the right side is a capacitor upper electrode.
After the gate electrodes and capacitor upper electrodes are patterned, the gate insulting films 103 are patterned wider than the electrodes 104 by photolithography and etching.
As shown in FIG. 23C, a photoresist pattern PRn is formed covering the p-channel transistor and opening the n-channel transistor and supplemental capacitor, and P+ ions are implanted at two steps. One ion implantation is performed at an acceleration energy and a dose which allow ions to be implanted into the exposed silicon film and does not allow the ions to be implanted into the electrode 104 and insulating film 103 not to reach the semiconductor layer. The other ion implantation is performed under the condition which allows some of the ions implanted into the insulating film 103 to pass through the insulating film 103 and reach the semiconductor layer 102 to form ion implanted regions of a low impurity concentration.
In this manner, low concentration drain regions LDD are formed under the gate insulating film on both sides of the gate electrode and high concentration drain regions HDD are formed on both sides of the gate insulating film. Thereafter, the photoresist pattern PRn is removed.
As shown in FIG. 23D, a photoresist pattern PRp is formed covering the n-channel transistor and supplemental capacitor and opening the p-channel transistor, and p-type impurities such as B+ ions are implanted at two steps.
One ion implantation is performed under the conditions that only the ions directly implanted into the semiconductor layer 102 are doped in the semiconductor layer and the impurities implanted into the electrode 104 and insulating film 103 do not reach the semiconductor layer 102. The other ion implantation is performed under the conditions that some of the impurities implanted into the insulating film 103 pass through the insulating film 103 and reach the semiconductor layer 102 to form low impurity concentration regions.
Since the LDD regions are not necessarily required in the p-channel transistor, the ion implantation may be performed once under the conditions of an acceleration energy and a dose allowing to achieve a desired high concentration, without forming the LDD regions. The photoresist pattern PRp is thereafter removed.
As shown in FIG. 23E, on the substrate subjected to the ion implantation, an SiO layer of 60 nm in thickness is deposited by CVD using Si source gas such as silane and O source gas such as oxygen, and an SiN layer of 360 nm in thickness is deposited by CVD using Si source gas such as silane and N source gas such as NH3, to thereby form a first interlayer insulating film 108.
After the first interlayer insulating film 108 is formed, annealing is performed for 2 hours at 550° C. to activate the implanted impurity ions. During this annealing process, hydrogen is dissociated from the SiN layer formed by the hydrogen-containing source gas such as NH3, so that the hydridation process of the semiconductor layer is performed.
Instead of thermal annealing, activating impurities may be performed by laser annealing and thereafter by annealing at 360° C. to perform the hydridation process of the semiconductor layer.
After the hydridation process of the semiconductor layer, a resist pattern is formed on the first interlayer insulating film 108 and etched to form openings therethrough to open desired areas of the semiconductor layer 102.
As shown in FIG. 23F, a Ti layer of 100 nm in thickness, an Al or Al alloy layer of 200 nm in thickness and a Ti layer of 50 nm in thickness are deposited by physical vapor deposition (PVD) to form an electrode layer. A resist pattern is formed on the electrode layer and etched to leave electrode/wiring patterns 109 leading desired regions of the semiconductor layer 102 to the upper surface of the first interlayer insulating film 108. The resist pattern is thereafter removed.
As shown in FIG. 23G, a transparent insulating resin layer of 3 μm in thickness covering the wiring patterns 109 is formed on the first interlayer insulating film 108 to thereby form a second interlayer insulating film 110. Contact holes are formed through the second interlayer insulating film by photolithography and etching, to expose the wiring patterns 109. If photosensitive resin is used as the second interlayer insulating film, contact holes can be formed by exposing and developing the second interlayer insulating film.
An ITO layer of 100 nm in thickness is deposited by PVD, being connected to the wiring patterns 109 exposed in the openings. The ITO layer is patterned by photolithography and etching to form a pixel electrode 111. The pixel electrode 111 is connected to the source/drain region of the n-channel TFT functioning as the switching transistor of the pixel, and to one electrode 102 of the supplemental capacitor. The other electrode 104 of the supplemental capacitor constitutes the supplemental capacitor bus line. In this manner, the p-channel TFT, n-channel TFT and supplemental capacitor SC can be formed.
It is preferable to shorten the channel length and dispensing with the LDD structure of a TFT which is required to operate at high speed. To this end, a circuit power source voltage is desired to be low. Generally, in order to lower the power source voltage, it is necessary to lower the threshold value of TFT and thin the gate insulating film. A high breakdown voltage TFT is required to be resistant against a predetermined high voltage, and has preferably the TFT structure having a conventional gate insulating film thickness and LDD structure. It is difficult to satisfy both the requirements by using the same TFT structure. Technologies of forming two types of TFTs on the same substrate have been proposed.
Japanese Patent Laid-open Publication No. 2003-45892 proposes the structure that after an island semiconductor layer is formed, a first gate insulating film suitable for low voltage TFTs is formed, a gate electrode is formed on the island semiconductor layer for the low voltage transistor, whereas for the high voltage transistor and pixel transistor, a second gate insulating film is stacked on the first gate insulating film and a gate electrode is formed on the second gate insulating film. The first gate insulating film of the low voltage transistor is, for example, 30 nm in thickness, and the gate insulating film of the high voltage transistor as a lamination of the first and second gate insulating films is, for example, 130 nm in thickness.
In order to further sophisticate the performance of TFT, new crystallization technologies have been proposed.
Japanese Patent Laid-open Publication No. 2003-86505 proposes the technologies of patterning an amorphous silicon semiconductor layer in an island shape, and thereafter polycrystallizing the semiconductor layer by irradiating from the bottom of a transparent substrate a continuous wave (CW) laser beam using a solid state laser excited by a laser diode semiconductor; a diode pumped solid state laser (DPSS laser). This publication describes that large crystal grains can be formed by this crystallization method.
In the TFT manufacture processes, impurities are activated by thermal annealing or laser annealing. The thermal annealing is desired to obtain a high reliability. If a high speed operation circuit is made of specific TFTs or crystallization is performed by a CW laser beam, the thermal annealing is desired to be used for annealing impurities.
If thermal annealing is to be performed, it is not proper to use aluminum or aluminum alloy as the metal wiring, but refractory metal is required to be used. Refractory metal has a higher resistance than that of aluminum or aluminum alloy and there arises the problem of a high wiring resistance of a large size panel. If the display device is of a high definition type, it is desired to reduce the area of a supplemental capacitor.